Salam semua...
hr ni pg class tuk fyp lg tp skng dh tukar time pagi (10.30am - 12.30pm)
ok la skt...class pg2 mcm ni kurang skt ngantuk..huhu
kalo ptg2 or mlm2 muka msing2 x bley bla especially aku la...hahaha
ngantuk thap cipan nk beranak...
pg td aku la org 1st kene present about ISE design flow...
my part are about creating the design and synthesis...
actually it is not really presentation...huhu..
sbb mcm dah membace je..huhu
but sir really like it...huhu..
he's appreciate our job...(good job shahida...sir said) =p
and good job for pae n ina also...fatra not yet (dia x present lg) =p
bgus jgk wat mcm ni, kalo x mmg lngsung x phm pape...
what is ISE?
what is DSP?
what is FPGA?
what...why...how...when...to use all those thing?????huhu...
from now on we need to learn about electronic part...
the transistor, capacitor, resistor, semiconductor, and also sequential gate...
for next week continue the presentation and discuss about the electronic part
then go to the basic of radar...
but the problem is to download the ISE software from xilinx website it very challenging part...
it takes 2 day for complete downloading n installing the software about 8GB...
but it's still depends on the speed of ur computer and also about firewall that make it slow...
this is what we need to pay (for time) bcoz we are using free wireless...huhu
another problem is the software is not compatible with vista =(
so by hook or by crook we all need to install XP for this project...
bcoz of that, my laptup has 3 OS ( vista, ubuntu n XP)...
rase mcm nk tmbah lg stu which is fedora...huhu..tamak sungguh..hehe
(lenovo bertahan la kamu eh selagi aku x hbs study ni...luv u lenovo...hehe)
then stu lg, my language will plus one more...hehe
my new language is verilog...hehe(try to luv it..huhu)
ok la nnt aku story lg...
*these pic bout my fyp
hr ni pg class tuk fyp lg tp skng dh tukar time pagi (10.30am - 12.30pm)
ok la skt...class pg2 mcm ni kurang skt ngantuk..huhu
kalo ptg2 or mlm2 muka msing2 x bley bla especially aku la...hahaha
ngantuk thap cipan nk beranak...
pg td aku la org 1st kene present about ISE design flow...
my part are about creating the design and synthesis...
actually it is not really presentation...huhu..
sbb mcm dah membace je..huhu
but sir really like it...huhu..
he's appreciate our job...(good job shahida...sir said) =p
and good job for pae n ina also...fatra not yet (dia x present lg) =p
bgus jgk wat mcm ni, kalo x mmg lngsung x phm pape...
what is ISE?
what is DSP?
what is FPGA?
what...why...how...when...to use all those thing?????huhu...
from now on we need to learn about electronic part...
the transistor, capacitor, resistor, semiconductor, and also sequential gate...
for next week continue the presentation and discuss about the electronic part
then go to the basic of radar...
but the problem is to download the ISE software from xilinx website it very challenging part...
it takes 2 day for complete downloading n installing the software about 8GB...
but it's still depends on the speed of ur computer and also about firewall that make it slow...
this is what we need to pay (for time) bcoz we are using free wireless...huhu
another problem is the software is not compatible with vista =(
so by hook or by crook we all need to install XP for this project...
bcoz of that, my laptup has 3 OS ( vista, ubuntu n XP)...
rase mcm nk tmbah lg stu which is fedora...huhu..tamak sungguh..hehe
(lenovo bertahan la kamu eh selagi aku x hbs study ni...luv u lenovo...hehe)
then stu lg, my language will plus one more...hehe
my new language is verilog...hehe(try to luv it..huhu)
ok la nnt aku story lg...
*these pic bout my fyp
ISE Design Flow
DSP slice architecture
A DSP48 Tile Consisting of Two DSP48 Slices
~~~laugh is the best medicine~~~
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